NUMERICAL SIMULATION OF NANOSCALE DOUBLE-GATE MOSFETS

ABSTRACT The further improvement of nanoscale electron devices requires support by numerical simulations within the design process. After a briefly description of our 2D/3D-device simulator SIMBA, the results of the simulation of DG-MOSFETs are represented. Starting from a basic structure with a gate length of 30 nm, a calibration of model parameters was done based on measured values from literature. Afterwards a variation of gate length, channel thickness and doping, gate oxide parameters and source/drain doping was carried out in connection with the numerical calculation of device characteristics. Thereafter an optimization of a DG-MOSFET with a gate length of 15 nm was done. The optimized structure shows suppressed short channel behavior and short switching times of about 0.15 ps.


INTRODUCTION
Double-Gate (DG) MOSFETs are considered to be one promising candidate for nanoscale CMOS.The International Technology Roadmap for Semiconductors (2005 Edition) predicts printed gate lengths up to 15 nm for the next 10 years.For these gate lengths conventional MOSFETs are limited due to different short channel effects.On the other hand structures with two gates and extremely thin body demonstrate a better control of the gate region and consequently a suppression of short channel effects.Numerical device simulation is an important procedure for the design and optimization of novel semiconductor devices.Advantages are the calculation of the electrical behavior before the fabrication process, the calculation and visualization of inner-electronic values which are not measurable, the diagnosis/fault-detection in the technological process and consequently the cost efficiency.

SIMULATION MODELS
The quantum hydrodynamic (QHD) models , which are based on a quantum fluid dynamic model, offers expanding possibilities for the understanding as well as the design of quantum sized semiconductor devices.The advantage of this model is its macroscopic character, which enables to obtain description without knowledge of quantum mechanical details like initial wave function [1], [2], [3].The classical hydrodynamic (HD) model for the semiconductor device simulation can be extended by expressions in the transport and in the energy balance equations They describe an internal quantum potential in the transport equation as well as a quantum heat flux in the energy balance equation.These additional terms in the classical hydrodynamic model allow to describe continuous electron and hole distribution in a semiconductor device, accumulations of carriers in potential wells and resonant tunneling of carriers, respectively.The standard model for universal device simulations is the driftdiffusion (DD) model, which can be derived from the above mentioned model [4].Basic equations of the QHD model are the Poisson equation continuity equations (index p: holes, index n: electrons) energy flux density equations ( ) ( ) and equations for the quantum correction potential Further approaches are necessary for carrier mobilities, generation and recombination rates, diffusion coefficients and energy relaxation times, which are almost material dependently.Equations ( 1) to (11) are solved self-consistently for the variables (ϕ, p, n, T p , T n , λ p , λ n ).If equations ( 10) and ( 11) are neglected, that means for λ p , = λ n = 0, QHD model can be reduced to the conventional hydrodynamic (HD) model.If carrier temperatures are set to lattice temperature and equations ( 6) to (9) are neglected, the quantum drift diffusion (QDD) model and additionally for λ p = λ n = 0 the conventional drift diffusion (DD) model can be obtained.Solution of the equations are achieved by a successive algorithm (so called Gummel algorithm).For the solution of the partial differential equations a box method is used.The resulting non-linear equation systems are solved by the NEWTON-method and corresponding linear equation systems by preconditioned gradient methods.All models are implemented full three-dimensional in the program system SIMBA [5] [6].

BASIC STRUCTURE SIMULATION AND VERIFICATION
Starting point of the simulations is a basic structure, represented in Figure 1, as functional relevant detail of the real device.The different parameters are assumed as following: gate length L G = 30 nm, source/drain lengths L S = L D = 100 nm, gate-to-source and gate-to-drain distances L GS = L GD = 100 nm, silicon film thickness T Si = 20 nm, gate oxide thickness T ox = 2 nm, channel doping N A = 1⋅10 16 cm -3 , source/drain doping N D = 3⋅10 20 cm -3 .The simulated output characteristics drain current I D versus drain-to-source voltage V DS are plotted in Figure 2 for different gate-to-source voltages V GS .Verification of the simulation results and calibration of the model parameters were done by comparison with experimental values from [7].A structure similar to Figure 1 with L G = 45 nm, T ox = 2.5 nm, N D = 2⋅10 20 cm -3 was simulated and compared with the measured values.The results represented in Figure 3 show a good agreement.A further successful verification was done by results from [8]. (µA/µm)

PARAMETER VARIATION AND OPTIMIZATION
To study the influence of the structure parameters on the electrical device characteristics different parameters are modified.In Figure 4 and 5 the output and the transfer characteristics at different gate lengths are depicted.At shorter gate lengths a threshold voltage roll off can be observed as a typical short channel effect in particular pinch-off behavior disappears for L G < 30 nm.At the same time drain saturation current increases strongly.Variation results of the silicon film thickness are represented in Figure 6.Thicker channels lead to larger drain currents but also to a displacement of the threshold voltage toward smaller values.Therefore the film thickness should be not larger than 20 nm.Thinner gate oxides result in increasing drain currents (Figure 7) and transconductances and in a better pinch-off behavior.According to that the smallest possible oxide thickness should be applied.Variation of the channel doping causes a decrease of the drain current for doping densities greater than 10 17 cm -3 (Figure 8).Furthermore the threshold voltage is strongly influenced by doping changes.For optimization of the structures, channel doping can be used to adjust the required threshold voltage.The source/drain doping should be high enough to reduce series resistances whereas the dopant diffusion into the channel has to minimize to prevent short channel effects.In this case rapid thermal annealing processes are an essential requirement.Figure 9 shows the corresponding output characteristics.The knowledge from different variations was used for the design of an optimized structure.A minimal technologically practicable gate length of L G = 15 nm and a gate oxide thickness of T ox = 1.5 nm are specified.Further objectives are threshold voltage of V Th = 0.1 V, large drain saturation current and improved dynamical behavior.After several iterations the further parameters are determined as follows: T Si = 3 nm, N A = 2.8⋅10 19 cm -3 , N D = 7⋅10 20 cm -3 .The resulting output characteristics are represented in Figure 10. Figure 11 shows the comparison between transfer characteristic of the optimized and basic structure.An enlarged drain current as well as an improved transconductance can be observed.For the determination of the dynamical behavior the gate-to-source voltage was switched from 0 V to 1 V to find the turn-on time ( t ON ) and from 1 V to 0 V to find the turn-off time ( t OFF ). Figure 12 shows the time response of the drain current.Therefrom the switching times result to t ON = t OFF = 0.15 ps.Compared with the basic structure the switching times are reduced by the factor 0.6 due to the structure reduction primarily.

CONCLUSION
The scaling down of planar bulk MOSFETs according the International Technology Roadmap for Semiconductors requires new structures such as multiple-gate MOSFETs.One of the promising possibilities are double-gate transistors.The implementation will be challenging with numerous new and difficult issues.In this case numerical device simulation is essential.Variations of different structure parameters have been carried out to calculate the influence on device characteristics.Based on these results an optimized structure with a gate length of 15 nm was created.The optimized structure shows suppressed short channel effects and switching times of about 0.15 ps.

Fig. 8 :
Fig. 8: Output characteristics at different channel doping Fig. 9: Output characteristics at different source/drain doping

Fig. 10 :
Fig. 10: Output characteristics of the optimized structure Fig. 11: Transfer characteristics of the basic and the optimized structure

Fig. 12 :
Fig. 12: Switching behavior of the optimized structure