MODEL-BASED SECURITY ANALYSIS OF FPGA DESIGNS THROUGH REINFORCEMENT LEARNING

Authors

  • Michael Vetter University of West Bohemia

DOI:

https://doi.org/10.14311/AP.2019.59.0518

Keywords:

FPGA, IT security, model-driven design, reinforcement learning, machine learning.

Abstract

Finding potential security weaknesses in any complex IT system is an important and often challenging task best started in the early stages of the development process. We present a method that transforms this task for FPGA designs into a reinforcement learning (RL) problem. This paper introduces a method to generate a Markov Decision Process based RL model from a formal, high-level system description (formulated in the domain-specific language) of the system under review and different, quantified assumptions about the system’s security. Probabilistic transitions and the reward function can be used to model the varying resilience of different elements against attacks and the capabilities of an attacker. This information is then used to determine a plausible data exfiltration strategy. An example with multiple scenarios illustrates the workflow. A discussion of supplementary techniques like hierarchical learning and deep neural networks concludes this paper.

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Author Biography

Michael Vetter, University of West Bohemia

Michael Vetter is a PhD student at the University of West Bohemia.
His research interests are in the areas of IT security and Model Driven Engineering,
with the focus on FPGAs and Embedded Systems.

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Published

2019-11-01

How to Cite

Vetter, M. (2019). MODEL-BASED SECURITY ANALYSIS OF FPGA DESIGNS THROUGH REINFORCEMENT LEARNING. Acta Polytechnica, 59(5), 518–526. https://doi.org/10.14311/AP.2019.59.0518

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Section

Articles