High Performance IIR Filter FPGA Implementation Utilizing SOS Microcode Core
DOI:
https://doi.org/10.14311/TEE.2019.2.022Abstract
This paper discusses the methods of optimal IIR filter FPGA implementation. The methods are focused on the reduction of occupied resources and increasing data throughput. Higher demands on an internal controller complexity are successfully solved by utilizing programmable microcode controller. The novelty of SOS core and its capabilities are presented and different variants of SOS core are assessed. The workflow of IIR filter design using MATLAB considering rounded coefficient method is demonstrated.References
R. Landry, V. Calmettes and E. Robin, “High speed IIR filter for XILINX FPGA,” in 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268), Notre Dame, IN, 1998, pp.46-49.
S. T. Pan, “Evolutionary Computation on Programmable Robust IIR Filter Pole-Placement Design,” IEEE Transactions on Instrumentation and Measurement, vol. 60, no.4, pp.1469-1479, April 2011. https://doi.org/10.1109/TIM.2010.2086850
R. G. Lyons, “Infinite impulse response filters,” in Understanding digital signal processing, 2nd ed., New Jersey, USA: Pearson Education Inc. 2008, ch. 6, pp. 211–282.
U. Meyer-Baese, “Infinite impulse response (IIR) digital filters,” in Digital signal processing with Field Programmable Gate Arrays, 4th ed., Heidelberg, Germany: Springer-Verlag Berlin Heidelberg. 2014, ch. 4, pp. 225–304.
