Finite Automata Implementations Considering CPU Cache

J. Holub

Abstract


The finite automata are mathematical models for finite state systems. More general finite automaton is the nondeterministic finite automaton (NFA) that cannot be directly used. It is usually transformed to the deterministic finite automaton (DFA) that then runs in time O(n), where n is the size of the input text. We present two main approaches to practical implementation of DFA considering CPU cache. The first approach (represented by Table Driven and Hard Coded implementations) is suitable forautomata being run very frequently, typically having cycles. The other approach is suitable for a collection of automata from which various automata are retrieved and then run. This second kind of automata are expected to be cycle-free. 

Keywords


deterministic finite automaton; CPU cache; implementation

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This work is licensed under a Creative Commons Attribution 4.0 International License.

ISSN 1210-2709 (Print)
ISSN 1805-2363 (Online)
Published by the Czech Technical University in Prague