VERSATILE CHIRP SINE GENERATOR ON FIXED-POINT FPGA

Authors

  • Jan Kunz Brno University of Technology, Faculty of Electrical Engineering and Communication, Department of Control and Instrumentation, Technická 3082/12, 61600, Brno, Czech Republic https://orcid.org/0000-0002-6917-7950
  • Petr Beneš Brno University of Technology, Faculty of Electrical Engineering and Communication, Department of Control and Instrumentation, Technická 3082/12, 61600, Brno, Czech Republic

DOI:

https://doi.org/10.14311/AP.2020.60.0462

Keywords:

Linear Chirp Sine, logarithm chirp sine, FPGA, fixed-point, generation

Abstract

This paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.

References

R. L. Allen, D. W. Mills. Time, Frequency, Scale and Structure. John Wiley & Sons, Inc., 2004.

IEC:60068-2-6. Environmental testing: Tests – Test Fc: Vibration (sinusoidal), 2nd edn., 2007.

J. Vankka, K. A. Halonen. Direct digital synthesizers: theory, design and applications, vol. 614. Springer Science & Business Media, 2013.

E. Murphy, C. Slattery. Ask the application engineer—33 all about direct digital synthesis. Analog Dialogue 38(3):8 – 12, 2004.

U. Meyer-Baese. Digital signal processing with field programmable gate arrays, vol. 2. pringer, 2004.

National Instruments. CompactRIO Systems. https://www.ni.com/cs-cz/shop compactrio.html.

S. Srivastava, P. Hobden. 5Ghz Chirp Signal Generator for Broadband FMCW Radar Applications. In 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp. 152 – 155. 2018. doi:10.1109/iSES.2018.00041.

H. Yang, S.-B. Ryu, H.-C. Lee, et al. Implementation of DDS chirp signal generator on FPGA. In 2014 International Conference on Information and Communication Technology Convergence (ICTC), pp. 956–959. IEEE, 2014. doi:10.1109/ICTC.2014.6983343.

H. Yang, S.-B. Ryu, H.-C. Lee, et al. Implementation of DDS chirp signal generator on FPGA pp. 956–959, 2014. doi:10.1109/ICTC.2014.6983343. [10] M. Y. Chua, J. T. Sri Sumantyo, Y. Q. Ji. An 8- Channels FPGA-Based Reconfigurable Chirp Generator for Multi-Band Full Polarimetric Airborne/Spaceborne CP-SAR. In 2018 Progress in Electromagnetics Research Symposium (PIERS-Toyama), pp. 876–881. 2018. doi:10.23919/PIERS.2018.8597713.

J. An, H. Jung, H. Yang, et al. Development of chirp signal generator for micro satellite on-board synthetic aperture radar. In 2015 IEEE International Geoscience and Remote Sensing Symposium (IGARSS), pp. 3663–3666. IEEE, 2015.

H. Yang, Y. Izumi, A. Hendra, J. T. S. Sumantyo. Novel chirp phase error compensation algorithm using polynomial chirp modeling for high resolution synthetic aperture radar. In 2017 IEEE International Geoscience and Remote Sensing Symposium (IGARSS), pp. 6012–6015. 2017. doi:10.1109/IGARSS.2017.8128380.

Intel. Nco ip core: User guide. https: //www.intel.com/content/dam/www programmable/

us/en/pdfs/literature/ug/ug_nco.pdf, 2017. Accessed: 16 September 2020.

XILINX. Dds compiler v6.0. https://www.xilinx. com/support/documentation ip_documentation/dds_ compiler/v6_0/pg141-dds-compiler.pdf, 2017. Accessed: 16 September 2020.

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Published

2020-12-31

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Articles