PVT-aware, low-leakage CNFET SRAM with enhanced stability for MIMO systems

Authors

  • Manickam Kavitha Government College of Engineering-Bargur, Department of ECE, 635104 Tamilnadu, India
  • Ramani S. Sreenidhi Institute of Science and Technology, Department of ECE, 501302 Hyderabad, India
  • Sundaravanan Jothiprakasam Thanthai Periyar Government Institute of Technology, Department of ECE, Vellore, 632002 Tamilnadu, India
  • Ramakrishnanan Ranjith Government College of Engineering-Srirangam, Department of ECE, 620012 Tamilnadu, India
  • Janani P. K. Anna University, Faculty of Science and Humanities, 600025 Tamilnadu, India

DOI:

https://doi.org/10.14311/AP.2026.66.0036

Keywords:

carbon nanotubes (CNT), CNFET, SRAM, low power, VLSI, MIMO

Abstract

The increased use and commercialisation of portable battery powered electronic gadgets has made low-power chip designs essential for extending battery life. Low-power electronic circuits also play an important role in the emerging wireless communication systems. Designing appropriate memory circuits is the key for the aforementioned cases, as memory occupies most of the chip area. In this paper, CNFET (Carbon Nanotube Field Effect Transistor)-based low-leakage SRAM (Static Random Access Memory) with enhanced stability is proposed. Simulations are carried out for the proposed CNFETSRAM cell, and its performance is compared with the conventional structures in terms of power, delay, stability, and power delay product by varying PVT (process-voltage-temperature) parameters. According to the results, the hold, read and write stability of the proposed CNFET SRAM improved by 49 %, 85% and 56 %, respectively, as compared to existing memory cells. Furthermore, the hold or leakage power is minimised by up to 99 % compared to conventional SRAMs. The simulation results confirm that the proposed solution is an appropriate memory structure for MIMO systems, meeting the requirements for very large-scale integration (VLSI) circuits with low leakage and high stability.

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Published

2026-03-16

Issue

Vol. 66 No. 1 (2026)

Section

Articles

License

Copyright (c) 2026 Manickam Kavitha, Ramani S., Sundaravanan Jothiprakasam, Ramakrishnanan Ranjith, Janani P. K.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Kavitha, M., S., R., Jothiprakasam, S., Ranjith, R., & P. K., J. (2026). PVT-aware, low-leakage CNFET SRAM with enhanced stability for MIMO systems. Acta Polytechnica, 66(1), 36-46. https://doi.org/10.14311/AP.2026.66.0036